1. Field of the Invention
The present invention is directed to a large scale integrated circuit (LSI) which includes gate array circuits comprising MIS (metal insulator semiconductor) or CMIS (complementary MIS) type FETs (field effect transistors). More particularly, the present invention is directed to an output buffer circuit of a gate array. The present invention is intended to reduce noise induced by high current variations, or to stabilize a fluctuation of ground, both of which are caused by switching between output buffer circuits.
2. Description of the Prior Art
General LSIs are provided with input buffer circuits (or level shifters) which equalize signal levels of input signals to inner logic circuits or equipment. Recently, as the scale of integration in LSI circuits has become large, the number of gates included in an LSI circuit exceeds a few tens of thousand of gates per chip, and the number of output gates exceeds a few hundred. The output buffer circuit requires a high switching speed and driving capacity in order to drive various kinds of external loads. A noise problem exists, which is induced by a high switching current of the output circuit. Noise is becoming a serious problem for LSI or VLSI (very large scale integration) circuits, which are designed to operate with very small current.
In order to render clearly set forth the advantage of the present invention, prior art output buffer circuits and their design concepts will be described briefly. Circuit diagrams for some exemplary output gate circuits are shown in FIGS. 1 through 3. FIG. 1 is a non-inverting output buffer circuit, FIG. 2 is an inverting output buffer circuit and FIG. 3 is a NAND type output buffer circuit exemplifying an output buffer circuit coupled with a NAND gate. Throughout FIGS. 1-3, (a) is a symbol mark of the circuit and (b) is a circuit diagram of the inner connections of the gate circuit. In FIGS. 1-3, IN designates an input terminal which connects the gate circuit to the inner logic circuit, OUT is an output terminal, and G.sub.1 is a driver gate for an output buffer gate circuit G.sub.2. V.sub.DD is a high voltage source and V.sub.SS is a low voltage source (usually earth potential). As can be seen in the figures, the output buffer gate circuit G.sub.2 consists of a complementary MOS (CMOS) circuit comprising a p-channel MOS (p-MOS) FET T.sub.1, and an n-channel MOS (n-MOS) FET T.sub.2.
The driving force or driving capacity of the output buffer circuit is determined by the output impedance or mutual conductance gm of the CMOS FETs T.sub.1 and T.sub.2. The following relation is known in the art: ##EQU1## where .beta. is the current amplification factor of the transistor, W is the gate width of the FET, and L is the gate length of the FET. Therefore, a high driving capacity of the output buffer circuit is attained by shortening the gate length L and making W large, that is, elongating the transistor.
In prior art LSI devices the ratio W/L of transistors for an inner gate G.sub.0, for the driving gate G.sub.1, and for the output buffer gate G.sub.2 are determined respectively as, for example, 1:3:10 or 1:5:20, during the design stage of the LSI device. These ratios are determined to minimize the chip area, or to minimize the switching time of the output buffer gates.
Recently there appeared some attempts to optimize the size of the output buffer circuit and its driving stage. For example, Japanese Provisional Publication No. 57-148363 by K. Kinoshita (laid open on Sep. 9, 1982) or No. 58-127347 by S. Wakamatsu (laid open on Jul. 29, 1983) show some of them. These references attempt to optimize the output circuit introducing the idea of master slice technology, that is, a plurality of transistors (FETs) having predetermined sizes (for example three sizes having a size ratio of 1:2:3) are fabricated at the I/O (input/output) circuit area of an IC chip, and they are properly connected by a wiring pattern.
FIGS. 4(a)-4(c) illustrate this idea. In FIG. 4(a), part of the I/O area which is generally located at the peripheral part of the chip is shown. As shown in FIG. 4(a), 11 are the smallest size FETs, 12 are the second size FETs whose size is twice of that of FETs 11, and 13 are the largest FETs (three times as large as FETs 11). If two fan out circuits or three fan out circuits are required as shown in FIG. 4(b) or 4(c), proper size FETs are selected and connected to each other as shown. For example, for a two fan out circuit the second size FET 15 is used to drive two small size FETs 14. For a three fan out circuit, the largest size FET 17 is used to drive three small FETs 14. In such a manner, a decrease in the switching speed is prevented.
As has been described above, prior art output gate circuits are designed to operate as fast as possible. The high speed and high driving capacity of the output buffer circuit is attained by increasing the switching current handled by output transistors. High current switching has increased the problem of induced noise, especially for very large scale integrated circuits (VLSI). The inner logic circuit, which is a main part of the logic circuit, is designed to work with a current as small as possible to prevent heat dissipation, but the output circuit cannot cut down the switching current to drive outer circuit which generally has a large stray capacitance. Moreover, as the number of output buffer circuits increases, there occurs a change that several output circuits work at the same instant, so the multiplied switching current induces noise in the wiring lines or pins in the package, and causes malfunctions in the device. This is becoming a serious problem for VLSI circuits.
The voltage fluctuation V.sub.N which appears on the V.sub.SS line is given as: ##EQU2## where R is the resistance of the wiring, L is the inductance of the V.sub.SS line and I is the current flowing in the V.sub.SS line. This voltage flucuation causes the noise and malfunction of the inner circuit. If the circuit is designed to have a large value of W/L in order to achieve a high switching speed or a high driving capacity, the current amplification factor .beta. becomes large since the current I is proportional to .beta., which is proportional to W/L.
There exists a trade off, therefore, between achieving a high speed switching or a high driving capacity and decreasing the switching noise. It is especially serious for LSI or VLSI circuits, wherein many of the output buffer circuits have a chance to work at the same time, and by the sum of the switching currents, noise is induced on the V.sub.SS line or on the V.sub.DD line, and a malfunction of the main logic circuit results.